1. Field
The present embodiments relate to a semiconductor memory having a main word decoder and sub word decoders to select word lines.
2. Description of the Related Art
In a semiconductor memory such as a DRAM, a word line is formed with a main word line and sub word lines directly coupled to a memory cell MC so as to reduce a resistance of the word line coupled to the memory cell MC and to improve an access speed. The main word line is wired to plural sub word lines in common, and it is selected by a main word decoder in accordance with an address signal. Any of the sub word lines corresponding to the selected main word line is selected by a sub word decoder in accordance with the address signal (for example, Japanese Laid-open Patent Publication No. 2003-109398).
For example, the sub word decoder has a CMOS inverter and a reset transistor (an nMOS transistor) coupled to an output of the CMOS inverter (sub word line). The CMOS inverter receives a control signal changing to high level/low level at a source of a pMOS transistor, couples an input terminal to the main word line, and couples a source of the nMOS transistor to a low-level power supply line. In the reset transistor, a drain is coupled to the sub word line, the source is coupled to the low-level power supply line, and a gate receives a signal in which the control signal is inverted.
The sub word line changes to high level when the control signal is high level and the main word line is low level, and the memory cell is accessed. Besides, when the control signal is low level or the main word line is high level, the sub word line changes to low level.
In the sub word decoder, when an on-resistance of the nMOS transistor of the CMOS inverter or of the reset transistor is high, the sub word line is reset to low level by only one of the low level of the control signal or the high level of the main word line. The above-stated on-resistance becomes high, for example, when a value of a source-resistance of the transistor is high or when a resistance of a contact coupling the source of the transistor to the low-level power supply line is high. When the resistance is not normal, there is a possibility in which the resistance increases gradually by continuously using the semiconductor memory. In this case, an operation failure (reliability failure) of the sub word decoder may occur.
However, it is difficult to detect an abnormal state of one of the resistances because the nMOS transistor of the CMOS inverter and the reset transistor may turn on at approximately the same timing.